1. Technical Field
The present disclosure relates to a phase frequency detector, and, more particularly, to a digital phase frequency detector (PFD), a digital phase locked loop (PLL) including the digital phase frequency detector and a method of digitally detecting a phase and a frequency of an output signal.
2. Discussion of the Related Art
A phase locked loop (PLL) is widely used to generate a signal having a fixed phase and a fixed frequency. A conventional PLL is implemented by analog circuits that include a phase frequency detector (PFD) which compares the phase of two input signals, a charge pump, a loop filter, a voltage controlled oscillator and a divider. However, the conventional analog PLL typically provides low accuracy and has high sensitivity to external noises. To avoid these analog circuit issues, a digital PLL that is implemented by digital circuits has been proposed. Usually, in the digital PLL, a digital PFD corresponding to the PFD of the analog PLL is used. The performance of the digital PLL depends upon the performance of the digital PFD. A need exists for a PFD that not only has a relatively small size and high operating speed, but can accurately detect the phase and frequency of an output signal.